Many integrated circuits or “chips” go into production and exhibit intermittent failure. If digital circuits are designed to use entirely synchronous logic, with only one clock, synchronisation issues are generally trivial. However, in the world of digital circuit design, designers are more often required to create multi-clock designs. Multi-clock implies that the design has at least two clocks, but possibly many more clocks, that are asynchronous. These digital designs will include at least one, though probably multiple signals that cross the boundaries between clock environments. If these signals are not adequately synchronised then the circuit will develop errors.
There are tools currently available that are designed to verify that timing constraints are met in a digital circuit when it is being designed and verified. These tools may be applied where there is a block of synchronous logic. However, they are impractical when there are multiple asynchronous clocks within a circuit as there are an infinite number of possible clock timings that must be evaluated.
If data is transferred from one clocked environment to another, then there may be signals that return to the original environment, perhaps in a handshake arrangement. These signals verify that data has been correctly received. All of these signals will also need to be adequately synchronised. It is possible that some signals that cross clock boundaries do not need synchronisation if they are controlled by another signal that has been synchronised.
Once a circuit has been designed it is important that it is tested to ensure that there is adequate synchronisation to avoid the propagation of metastable states through the circuit. Typically, the circuits are very large and so computer simulation methods are used to verify the design of the circuit. There are two techniques which are used for analysing circuits—firstly, dynamic timing analysis using fully timed simulation, and secondly, static timing analysis. However, neither technique is appropriate for determining if there is adequate synchronisation. Formal methods and/or property checking methods again, at present, do not provide useful information. This is because the amount of computer resource required would be much more than would be reasonable to use. In other words, these methods suffer from the problems that they are not practical, not commercially viable and/or do not provide the required results.